Radio Frequency Identification (RFID) Systems utilize “tags” which are attached to an object to be tracked and have been used in automated pay systems, and the tracking of animals or goods in inventory or in transit. These devices have been around since the 1970's but are burgeoning in the market because of the need for a system which tracks goods which does not need the direct contact that is required for a bar code reader, for example. Currently major retailers are planning on implementing the use of RFID tags on pallets in order to track inventory and plan to start using these on individual items, once the cost of the tags is reduced to about 5 cents per tag.
One way of reducing the cost per tag is to manufacture the tag so they take up very little real estate on the semiconductor wafer. Thus, tags will now be built using sub-micron (≦0.2 micron) CMOS technology. This results in a larger number of chips per wafer, and will enable the production of lower cost chips so that they can be more widely deployed.
Integrated circuit chips manufactured using sub-micron CMOS technology can not tolerate voltages above substantially 1.5 volts. In RFID tags that are built to operate off of the energy supplied by the radio frequency interrogation signal, the voltage induced in the tag can vary from zero volts when the radio frequency source is off to tens of volts when the tag is in close proximity to the interrogating transmitter. In addition, the voltage induced in the tag can be erratic as the tag moves in and out of proximity to the interrogating transmitter. This is a very different scenario than for battery operated systems, where a battery voltage may vary by a few volts over the life of the battery, but the variation will be relatively slow.
The received radio frequency signal from the interrogating transmitter is rectified to provide the power for the chip. FIG. 1 shows a crude clamp typically used in RFID systems at the output of the rectifier to provide a supply voltage VDD to the chip. The clamp has a series of diode connected transistors 102, 104, 106, 108 in series with the resistor 110 to ground. A diode connected transistor 112 is connected at the junction of transistors 104 and 106 to the gate of a bypass transistor 116 which is also connected via transistor 114 to the node between the source of transistor 108 and resistor 110. The gate of transistor 114 is tied to the node between transistors 106 and 108. When the current from the rectifier increases, the voltage drop across the resistor 110 increases, thereby increasing the voltage at node A and turning the bypass transistor 116 on strongly. The problem with this circuit is large variation, up to 1.5 volts, in the voltage VDD over process, temperature and radio frequency power variations. This variation is acceptable for certain technology, but will not be acceptable for deep sub-micron CMOS technologies because the maximum level of VDD is limited to 1.5 volts, and the circuits require 0.8 volts for proper operation.
A more accurate approach than the approach shown in FIG. 1 is shown in FIG. 2. The problem with the circuit shown in FIG. 2, is that at low values of current, the system is unstable. At low values of radio frequency power, the output resistance of the rectifier tends to be large and at high levels of radio frequency power, the resistance tends to be small. The loop gain can be expressed by the following:
                                          LG            ⁢                                                  ⁢            1                    =                                                                      gm                  ⁢                                                                          ⁢                  1                                                  sC                  ⁢                                                                          ⁢                  1                                            ·              gm                        ⁢                                                  ⁢                          2              ·              Zeff              ·              β                                      ⁢                                  ⁢                              Zeff            =                          Ra              ⁢                                                                (                                                            R                      ⁢                                                                                          ⁢                      1                                        +                                          R                      ⁢                                                                                          ⁢                      2                                                        )                                                            ⁢                              (                                  1                  sCL                                )                                              ,                      β            =                                          R                ⁢                                                                  ⁢                2                                                              R                  ⁢                                                                          ⁢                  1                                +                                  R                  ⁢                                                                          ⁢                  2                                                                                        Equation        ⁢                                  ⁢        1            
As shown by Equation 1, at low currents, Zeff is proportional to 1/(sCL) and the system has two poles and hence is potentially unstable. The only way to make the system more stable is to push the second pole farther away by decreasing the load capacitor CL. However, the load capacitor is utilized to supply current to the chip during times when no radio frequency power is being received, such as during a data “0”. Therefore, decreasing the capacitor is undesirable because it will result in the collapse of VDD to unacceptably low value during this time, which will reset the part. Furthermore, the response time of this circuit is very slow. Therefore, when there is a sudden burst of radio frequency energy, the Norton current source dumps current and tries to increase VDD. The slew rate (Itail/Cl) is a fixed low value which is limited by the tail current sink, and the bypass device is turned fully on very slowly. Meanwhile, the voltage VDD can increase to a level where certain devices connected to it will be damaged.